1. Field of the Invention
The invention relates generally to clock frequencies in processors and, more particularly, to hierarchical clock frequency domains for processor core logic functional units.
2. Description of the Related Art
Computers typically include a number of electronic circuits referred to as "clocks" that generate electrical "timing" or "clock" signals. Clock signals are used to control and coordinate the activities of the computer's various parts. One of the clock signals, the "system" clock signal, is a master clock signal to which the various parts of the computer synchronize their operation. The computer's parts frequently include "device" clocks generating a clock signal synchronized to the system clock. Because the device clocks are synchronized to the system clock, operations in the various parts can all be coordinated.
For instance, the computer might include a processor that directs the computer's operations and a memory controller that reads and writes information to and from a memory in response to directions from the processor. The computer generates the system clock signal that both the processor and the memory controller receive. The processor and memory controller usually run faster, i.e., operate a higher clock frequency, than does the system clock. To this end, the processor and memory controller include device clocks that generate a device clock signal synchronized to the system clock. The system clock signal therefore provides a common timing signal to which all the device clocks relate such that the operation of the various parts can be coordinated.
Many of the computer's parts, such as the processor itself, include, among other things, a number of logic units. Each logic unit performs some function necessary or desirable to the overall operation. In synchronous designs, the function of the logic units is also coordinated, or synchronized, by timing signals. However, at this level, all functions are typically performed relative to the device clock. The device generates the device clock and globally distributes it across the chip to all the core logic units. The functions of all the logic units can then be coordinated within the device since they are timed by the same clock signal.
Current techniques for fabricating synchronous devices such as processors have introduced new timing problems for device manufacturers. Evolving fabrication techniques have decreased the size of the devices and increased their operating speeds. Each generation of process technology seeks to increase the operating speed, i.e., frequency, while decreasing the size of the design. However, frequency does not necessarily scale upwardly as the size scales downwardly because of differing design factors.
Two factors affecting frequency are interconnect delay and logic gate delay. In synchronous designs, core logic units typically comprise state elements and logic elements. For instance, a core logic unit might comprise a latch through which data is input, several logic gates through which the input data is processed, and a latch through which the processed data is output. Each gate through which the data is processed introduces some amount of delay in the data throughput. This delay is the logic gate delay. The conductive material, or lines, through which the data is transmitted also introduces delay in the data throughput. This delay is known as the interconnect delay and varies depending on a number of factors such as the length and width of the lines.
The interconnect delay and the logic gate delay significantly impact the data throughput of the core logic unit. Further, the data typically must be processed through the logic unit in a single cycle of the device clock. Interconnect delay and logic gate delay therefore directly impact the frequency of the device clock by limiting it to the amount of time necessary to accomplish the data throughput. This problem is exacerbated in synchronous designs. Since all the logic units must synchronize their operation, they must receive input and output data at the same time regardless of how fast the data is processed. Thus, the logic unit with the fastest throughput can operate no faster than the logic unit with the slowest throughput.
One way to avoid some of this problem is to use asynchronous designs. In an asynchronous design, logic units are no longer required to synchronize their operations. The faster logic units are therefore free to operate at their individual data throughput. The faster logic units then have to wait on the slower logic units only periodically rather than at every clock cycle. However, asynchronous designs are very complex relative to synchronous designs. Asynchronous designs therefore are more expensive to design and manufacture. They also require larger amounts of space on the device. Since a device has only a limited amount of space in which to implement all its functions, asynchronous design can limit the performance of a device relative to a synchronous design. Asynchronous designs are therefore generally less acceptable than are synchronous designs.
Reducing interconnect and logic gate delay consequently intensely interests device designers. There are several satisfactory approaches to reducing logic gate delay, but the problem of interconnect delay has proven more intractable. Interconnect delay for the same line or net length does not decrease as the line width is scaled down to decrease size. The interconnect delay actually worsens. Existing solutions for the interconnect delay problem are all deficient in some respect and even the most promising of these solutions is viable for only a single processing generation.
Thus, the interconnect delay hampers the designer's ability to scale up the frequency at the same rate they scale down the size of the device. This fact, in turn, hampers efforts to increase overall performance in terms of size and speed. The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.